The present invention relates to a time base corrector for video signal, which corrects the change of time base contained in a video signal, and more particularly, to a time base corrector for video signal which forms a phase-locked loop to a chroma carrier and writes the result and modulates a read clock by using a difference of chroma carrier phase error between two serial lines to thereby compensate for a speed error.
FIG. 1 is a block diagram of a conventional time base corrector.
As shown in FIG. 1, a conventional time base corrector comprises a composite sync signal detector 1 for detecting the sync signal of an input analog video signal, an A/D converter 2 for converting the input analog video signal into a digital signal, a dropout corrector 3 for conforming the timing of the digital video signal output from A/D converter 2 according to an externally input dropout detection signal DOD, a FIFO memory 4 for storing the output of dropout corrector 3, a D/A converter 5 for converting the output of FIFO memory 4 into an analog video signal, a horizontal sync phase error detector 7 for detecting the horizontal sync phase error of the signal output from A/D converter 2, a chroma carrier phase error detector 6 for detecting the chroma carrier phase error of the signal output from A/D converter 2 by using the signal output from horizontal sync phase error detector 7, a phase detector 8 for selecting one of the signal output from chroma carrier phase error detector 6 and the signal output from horizontal sync phase error detector 7, two loop filters 9 and 10 for filtering the signal output from phase detector 8, a timing oscillator 11 for conforming the timing of the signal output from loop filter 10, a write clock generator 12 for generating a sampling clock of A/D converter 2 and a write clock of FIFO memory 4 according to the signal output from time oscillator 11, a sync separator 13 for separating a sync signal from the signal output from FIFO memory 4 and supplying a vertical sync signal V to phase detector 8, a linear interpolator 14 for linearly interpolating a horizontal sync signal H output from sync separator 13 and the signal output from phase detector 8, an operator 15 for 1/455 operating the signal output from linear interpolator 14, an integrator 16 for integrating the signal output from operator 15 and outputting the integrated signal to linear interpolator 14, a phase modulator 17 for phase-modulating the signal output from linear interpolator 14, and a read clock generator 18 for generating a read clock of FIFO memory 4 and a sampling clock of D/A converter 5 by using the signal output from phase modulator 17.
The operation of the conventional time base corrector for video signal will be explained below.
An input analog video signal is converted into a digital video signal of 8 bits in A/D converter 2 by taking the clock fed from write clock generator 12 as the sampling clock.
A 1H-preceding value of the video signal digitally converted in A/D converter 2 is latched in dropout corrector 3 according to externally input dropout detection signal DOD. The timing of the video signal is conformed in consideration of the phenomenon that the phase of chroma carrier is inverted for every line. Here, composite sync signal detector 1 separates the composite sync signal from the input analog video signal and supplies the separated signal to dropout corrector 3.
FIFO memory 4 stores the signal output from dropout corrector 3 in conformity with the write clock output from write clock generator 12 and reads out the signal in conformity with the read clock output from read clock generator 18. The read-out signal is supplied to D/A converter 5. The digital video signal output from FIFO memory 4 is converted into an analog video signal in D/A converter 5 according to the clock output from read clock generator 18.
Here, if jitter is contained in the input video signal, there are suggested two methods of generating a write clock varied according to the jitter. One is to fix it to a horizontal sync signal; the other is to fix it to the chroma carrier. The conventional time base corrector for video signal selectively uses the two methods.
In other words, the video signal output from A/D converter 2 is input to chroma carrier phase error detector 6 and horizontal sync phase error detector 7 to detect the chroma carrier phase error and horizontal sync phase error. The detected errors are supplied to phase detector 8 and selectively output.
The selection of phase detector 8 is performed with a signal JMP input to externally and forcibly indicate that there is a large time base error to the video signal, and a separated vertical sync signal V output from sync separator 13. The selection of the phase detector is performed by considering that there is no chroma carrier in the vertical sync section, and considering a case externally and forcibly indicating that there is a large time base error to the video signal.
During the vertical sync section and in the case externally and forcibly indicating that there is a large time base error to the video signal, phase detector 8 selects the horizontal sync phase error output from horizontal sync phase error detector 7. Otherwise, the phase detector selects the chroma carrier phase error output from chroma carrier phase error detector 6.
Here, sync separator 13 separates horizontal sync signal H and vertical sync signal V from a time-base-corrected composite sync signal out of the signals output from FIFO memory 4. Vertical sync signal V is supplied to phase detector 8 and horizontal sync signal H to linear interpolator 14.
The low-frequency component of the signal output from phase detector 8 is gain-controlled in loop filter 9 and input to the rear loop filter 10 which performs phase correction and gain control.
Here, since the horizontal sync phase error detected from horizontal sync phase error detector 7 is abnormally large, loop filter 10 receives a priority signal HI given to select the signal output from horizontal sync phase error detector 7 so as to select one of the signal output from the front loop filter 9 and the signal output from horizontal sync phase error detector 7.
The signal output from loop filter 10 is input to digital timing oscillator 11 and digital timing oscillator 11 oscillates to the frequency signal corresponding to the phase error, which is then supplied to write clock generator 12.
Write clock generator 12 generates a 4 fsc clock according to the signal input from digital timing oscillator 11 and supplies the clock to A/D converter 2 and FIFO memory 4. The clock is used as a sampling clock or write clock.
Even though the video signal is sampled with the variable 4 fsc clock obtained by the phase-locked loop, there is left a speed error present in 1H. Therefore, the signal output from the present phase error detector 8 and the signal output from 1H-preceding phase error detector 8 are interpolated in linear interpolator 14.
The signal output from phase detector 8 is latched by lines in linear interpolator 14 according to the horizontal sync signal H output from sync separator 13. The phase difference between two lines is sent to 1/455 operator 15 made up of a memory to obtain 1/455 the phase difference between the lines. The obtained value is integrated in integrator 16 so that a value accumulated every two clocks of 4 fsc is fed back to linear interpolator 14.
Linear interpolator 14 adds the signal output from integrator 16 to the 1H-preceding phase error and outputs the result so that in 1H the preceding error value reaches the present error value.
The output of linear interpolator 14 is input to phase modulator 17 to obtain a signal phase-modulated in proportion to the speed error present in one horizontal line. The obtained signal is converted into a read clock and amplified in read clock generator 18, and then supplied as the read clock of FIFO memory 4 and the sampling clock of D/A converter 5.
However, such conventional time base corrector for video signal has the following drawbacks:
First, the output of chroma carrier phase error detector 6 and the output of horizontal sync phase error detector 7 are switched.
Specifically, most of video signals are not linear-phase-processed in which group delay is fixed, so that the phase difference between the horizontal sync signal and chroma carrier is out of 0 degree. In this case, the reference phases of chroma carrier phase error detector 6 and horizontal sync error detector 7 are different. If so, switching for every vertical sync increases remaining jitter in the vertical sync. In order to solve this problem, the phase-locked loop is formed by the horizontal sync in the vertical sync section. Further, there is required a circuit for phase correction in consideration of the phase difference between the horizontal sync signal and chroma carrier in switching to chroma carrier phase error, or a circuit for shifting a sampling reference which takes, as the reference, the output of chroma carrier phase error detector 6.
Second, it is not desirable to phase-modulate the read clock with a linear phase interpolated value for the purpose of speed compensation.
In forming a circuit for phase-modulating the read clock with the linear phase interpolated value for the purpose of speed compensation, a digital phase modulator having a different configuration form the digital timing oscillator for forming the write clock requires a 1/455 divider or ROM and an integrator for accumulating two clocks of 4 fsc.